Just in case you are interested, uploaded the current (BASIC and
Hardware debugged) page on the 'Flash Attack Cable'. Still need to test
the VIC port Addresses (no biggie, does not affect the hardware) and
verify the ML (it's 9 years old, I know it worked then, but it was part
of alot more code) and fill in some blanks on the BASIC/KERNAL ML entry
points, start addresses, and USR() vectors.
Take a gander of it at:
http://www.jps.net/foxnhare/projects/facable.html
Any suggestions would be appreciated.
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Larry Anderson - Sysop of Silicon Realms BBS (209) 754-1363
300-14.4k bps
Classic Commodore pages at: http://www.jps.net/foxnhare/commodore.html
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