> On 2019-12-15, at 20:13, Frank Wolf <webmaster_at_frank-wolf.org> wrote: > >> Would that explain what Gideon experienced some time ago: >> "It was attempted to pull –DMA low around 250 ns before the falling edge of PHI2, so after the R/–W line had stabilized. This works perfectly on a 6510, but makes the 850x CPU in a C64c crash. Apparently, this CPU does not like to see RDY ‘true’ on a rising edge of PHI2, and ‘false’ on the subsequent falling edge." >> >> ? > > The reason for this behavior is caused by the way the RDY logic is implemented. It has nothing to do with the Port bits. I was not referring to port bits but to "side-by-side comparison of the 8500<->6510 [which shows that] they are 100% identical", which didn't refer to port bits either. IOW - this is a question if "100% identical [apart from the outer perimeter were the buffers/drivers reside]" refers only to port bits or to the whole chip. -- SD! - https://e4aws.silverdr.com/Received on 2020-05-29 23:56:15
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