Re: In search of bad 4164, 41256 DRAM

From: David Roberts <daver21145_at_gmail.com>
Date: Sun, 13 Oct 2019 22:46:00 +0100
Message-ID: <CAC5emFGHs=CfzU7-NJbDmKM8nYEJXdCT_w9WcsJa4hYW9GRHOw_at_mail.gmail.com>
One part of the test is an addressing error test. Another part is a 'stuck
at' test. The remainder of the tests generally test for interaction between
bits.

The MARCH tests treat all of the available memory as an 'array of bits' so
they can be used on bit-wide memory, byte-wide and word-wide of varying
widths. Incidentally, the B and C tests duplicate some tests, but the
remainder are unique.

Dave

On Sun, 13 Oct 2019 at 20:43, Jeffrey Birt <birt_j_at_soigeneris.com> wrote:

> Thanks Dave, I’ve read about the MARCH tests previously and to my
> understanding parts of these tests are designed to find addressing errors
> and/or for multi-bit wide memories. There is also the issue on modern
> processors with making sure that you just not writing/reading to/from cache.
>
>
>
> I did just finish up adding a ‘walking value’ test which fill the memory
> with all zeros or ones and steps through each bit, confirms it is still at
> the fill state, changes the state and tests for the changed state. This
> should hopefully help catch any internal addressing (row/column) errors
> where a write might write to adjacent cells as well.
>
>
>
> Now to clean up the code and update the schematic…
>
>
>
> Jeff Birt
>
>
>
> *From:* David Roberts <daver21145_at_gmail.com>
> *Sent:* Sunday, October 13, 2019 10:32 AM
> *To:* cbm-hackers_at_musoftware.de
> *Subject:* Fwd: In search of bad 4164, 41256 DRAM
>
>
>
> The MARCH-B and MARCH-C algorithms are described in
> http://ww1.microchip.com/downloads/en/Appnotes/00001778A.pdf with the
> actual fault scenarios being described in
> https://www.edn.com/design/integrated-circuit-design/4439803/Memory-fault-models-and-testing
> .
>
>
>
> Dave
>
>
>
>
>
>
>
Received on 2020-05-29 23:06:00

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