RE: In search of bad 4164, 41256 DRAM

From: Jeffrey Birt <birt_j_at_soigeneris.com>
Date: Sat, 12 Oct 2019 18:07:09 -0500
Message-ID: <000301d58151$c77a6900$566f3b00$_at_soigeneris.com>
Someone sent me some bad 4164 DRAMs which I tried in the DRAM tester this afternoon. This have proven to be very interesting. One of them tested bad on the first set of tests. A second one passed the first set of tests but failed every time there after when the tests were run again. The third one has been tested about 10 times now without fail.

The testing does not stress the DRAM as far as access time, the number of milliseconds it will retain data with no refresh etc. Actually, the refresh timer runs a little slower than the spec of 2ms but that has not been an issue. There might be temperature or voltage variations that effect the refresh time limit but that is beyond this simple tester.

Another interesting thing is that filling all cells with 1 or 0 seems to be a pretty poor way to test them. Failures how up much more readily when an alternating pattern is written. Writing the sequence of 0x55 or 0xAA seems to show failures where the filling of 1 or 0 might show no errors.

I'm going to add the ability to set the number of repetitions of the testing cycle. This might help weed out the chips like #2 above which tested OK the first time around.

Jeff Birt

-----Original Message-----
From: Francesco Messineo <francesco.messineo_at_gmail.com> 
Sent: Saturday, September 21, 2019 10:58 AM
To: cbm-hackers_at_musoftware.de
Subject: Re: In search of bad 4164, 41256 DRAM

On Sat, Sep 21, 2019 at 3:17 PM Jeffrey Birt <birt_j_at_soigeneris.com> wrote:
>
> -----Original Message-----
> From: Francesco Messineo <francesco.messineo_at_gmail.com>
>
> >>A common failure mode is the data I/O pins shorted to a power rail or not >>going to high impedance when the chip isn't addressed. So you must take >>care not to blow the driver pin to the data Input of the chip.
>
> 
Received on 2020-05-29 23:03:37

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