Re: In search of bad 4164, 41256 DRAM

On 9/14/19 6:20 PM, Jeffrey Birt wrote:
> I did some reading on these ‘march’ algorithms this morning and found 
> that a lot of the literature that is out there concerns byte/word wide 
> memories, testing memory in situ and weeding out all the other things on 
> a device (decoding logic, etc. ) that could cause problems.
> 
>  From what I can gather there is an issue where adjacent memory cells 
> can have an issue, i.e. if cell one is at a ‘1’ then cell ‘2’ might not 
> want to transition to a ‘1’ or ‘0’. The ‘marching’ are various bit 
> patterns to detect these types of errors with a minimum of time/effort 
> with different forms being better at detecting some types of faults than 
> others.

Also, back then, an empty DRAM cell didn't necessarily read as '0' to 
the outside. Take a look at the memory of a system that does not clear 
the RAM after power on. You'll notice a pattern that varies between 
manufacturers.

So, just writing a '1' and then waiting for it to fade to '0' if you 
stop refreshing will not work on all cells.

  Gerrit