Re: In search of bad 4164, 41256 DRAM

On 9/17/19 11:27 AM, smf wrote:
> On 17/09/2019 09:32, Gerrit Heitsch wrote:
>>
>> It should be since at power on the capacitor in a DRAM cell is empty
>> and if you stop refreshing it, it will also become empty after a
>> while. Whether this 'empty' is read as '1' or '0' depends on the
>> location on the die and on the manufacturer.
> 
> Can you explain why empty is read as 1 or 0 though? As far as I know
> dram cells are either empty or full and it checks if the cell is half
> full to work out the 0 or 1. So unless they randomly put inverters in
> there, an empty cell is an empty cell.

They seem to do exactly that. Otherwise it's not possible that you get a 
manufacturer specific pattern after power on.



> My thought was that during power on the dram is going to be unstable &
> it could generate the pattern if the dram did the equivalent of a
> refresh and the read part of it was done when there wasn't enough power
> to accurately determine the cell is empty enough while the write was
> done as the power stabilised. Maybe the power up ends up triggering a
> write without a read.

That should result in a more random pattern though.

But it should be easy to find out, hook a DRAM up to power and a CPU, 
read it out after power on. Then stop any refresh and any access for a 
while (minutes), and read it out again. If you get all zeros then there 
are no inverters. If you get a pattern again, there are inverters.

  Gerrit