Re: In search of bad 4164, 41256 DRAM

From: Mia Magnusson <mia_at_plea.se>
Date: Tue, 17 Sep 2019 19:02:23 +0200
Message-ID: <20190917190223.000039f6_at_plea.se>
Den Tue, 17 Sep 2019 18:27:39 +0200 skrev Gerrit Heitsch
<gerrit_at_laosinh.s.bawue.de>:
> On 9/17/19 6:19 PM, Mia Magnusson wrote:
> > That is simple to do on a PC/XT as you can control the refresh
> > circuit. You have to do some tricks though as a parity error on ram
> > read will trigger an NMI.
> 
> It also depends on the architecture. To do it correctly, you need at 
> least 2 memory banks that are not serviced by the same /RAS signal.
> Many systems run all RAMs on the same /RAS and select the banks with
> the /CAS signal. Unfortunatly, in this case, /RAS is all you need for
> refreshing a row and running your code in bank 0 will also refresh
> bank 1.

Well, assuming you can disable all interrupts so the CPU doesn't fetch
any data from low memory, you could put your idle code in the
graphics/display card ram. That would most likely make sure it won't
cause any RAS signals, unless the DRAM controller asserts RAS even for
addresses outside the DRAM area.

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Received on 2020-05-29 22:45:19

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