Re: 250466 PCB curiousness

On Fri, Jul 12, 2019 at 10:29 PM smf <smf_at_null.net> wrote:
>
> On 11/07/2019 16:14, Gerrit Heitsch wrote:
> > SRAM doesn't care what you do with the address lines during a read,
>
> It doesn't? AFAIK the memory is still organised in rows and columns, a
> read still opens a line and connects it to something that reads the line.
>
the difference is that SRAM just reads the state of a number of
flip-flops, read is non-destructive.
On the other hand, DRAMs do a read-write operation (also called
refresh when it's not triggered by a CPU actual read operation).
It means the charge of each cell (this time is a small capacitor, a
gate effectively) in the same row is amplified and written back on
each ROW access. So if the address setup time to the RAS falling edge
isn't satisfied, it can happen than part of a ROW is rewritten with
parts of another ROW.
Every DRAM access is a write access, there's no real "read" cycle. The
difference is between write and re-write, internally.
SRAM need no refresh, thus reads are never destructive.

HTH
Frank IZ8DWF