Am 1. Februar 2019 08:57:17 schrieb vossi <vossi@ceffy.de>: > Hi, > thanks Segher for the hint to the mcs6500 hardware manual. > I have it at home, but I never watched the addressing-cycles at the A-pages > ;) > > > The read before write is a normal (short) read-cycle, Andre - about 320ns at > 2MHz incl. the decoding logic in the 610. > > > RAM/ROM or mos IO chips doesn't matter about that none sense read. For some IO chips thus actually does matter. If, by unlucky coincidence the CIA IRQ flag register (IIRC) is read, you loose this information. I know this is an optimization that helps speed up IRQ handling, but also requires special handling if multiple, independently developed device drivers have to handle IRQs on the same chip. So I tend to like the VIA more, where you need to write to clear the IRQ flag, and you can do so for individual lines. André > But the V9938/58 increases mostly the VRAM addresscounter at this access... > > > I have an easy solution: > I split the write and read operations with A2. > So I have D900-D903 for write and D904-D907 for read. > A small 16V8 encodes now the CSW/CSR fro the VDP instead of the 7400. > > > Thanks > Christian > > > > > > > ----- > greets > Christian > -- > Sent from: http://cbm-hackers.2304266.n4.nabble.com/Received on 2019-02-01 10:00:03
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