Re: Interesting C64/6526 case

From: silverdr_at_wfmh.org.pl
Date: Fri, 26 Oct 2018 16:11:59 +0200
Message-Id: <4B68A8C0-39A6-4517-8F64-BC753A8FAC3E@wfmh.org.pl>
> On 2018-10-26, at 15:55, Francesco Messineo <francesco.messineo@gmail.com> wrote:
> 
> On Fri, Oct 26, 2018 at 3:49 PM <silverdr@wfmh.org.pl> wrote:
>> 
>> Now, we know those cases when the characters are garbled (not like garbage character but the character definitions are wrong). If not the CHAROM and not the CIA then the next goto chip is the U2 CIA. Checking the bits on its Port A is often enough to find that the lines read wrong combination, effectively preventing VIC from accessing the CHAROM. Now to the interesting case. I've got a CIA that passes all the diagnostic tests, including both ports. Moreover works all well everywhere (C64 U1, 1571) as long as it is not the U2 position in C64. There it causes the garbled characters symptom. Anyone willing to take a stab at possible explanation?
> 
> did you try to look at the actual signals with a scope?

Not yet. Just quickly exchanged chips around and checked how this behaves plus ran the diagnostics. I'll probably put up a scope on it over the weekend.

> I've found often that a failure mode of MOS Technology/CSG chips is a
> very weak pullup output capability on some output drivers.

The default is "Bank 0" so I guess it might rather be driving down problem, which in fact is what AFAIR NMOS drivers are not best at.

> It may work
> up to a reasonable logic level (2.5 - 3V) when driving few inputs or
> no inputs at all, and fall down to 2V or less when driving more stiff
> inputs or more inputs together.

Those lines have to drive 1 and 2 inputs only so that would mean that those inputs are more "stiff" in some way.

-- 
SD! - http://e4aws.silverdr.com/
Received on 2018-10-26 17:00:07

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