Re: Hardware emulation of 6509 using 6502?

From: Jim Brain <>
Date: Fri, 20 Jul 2018 13:35:27 -0500
Message-ID: <>
On 7/20/2018 1:43 AM, Baltissen, GJPAA (Ruud) wrote:
> Hallo Jim,
>>> The question is which devices do depend on this?
>> Ruud will have to answer.
> I only can give you two examples:
> - a memory expansion card for the ISA port with SRAM instead of DRAM. My 65816 equipped VIC-20 with ISA expansion would not recognize it.
> - my debugger, . It is able to single-step a computer. When stepping, it shows the momentary address and the data on the bus.
> In this case the data was garbled on the display although the VIC-20 ran fine. When I found out what the problem was and had it solved, the display wasn't garbled anymore and the card was recognized.
> OK, here was self-built hardware involved. But for me it was anyway a good lesson that if you emulate something, do that as good as possible.
A couple notes:

I know you mean no offense, but I do tend to take a bit of umbrage at 
the presumption that I am not doing a good enough job emulating past 

  * The only way to truly emulate the 6509 is to synthesize an FPGA core
    that runs at 100MHz or so and exactly matches the timings of the
    NMOS 6502 core (latency of signal changes, etc.), coupled with a set
    of buffer/driver/transceivers that exactly match the source and sink
    characteristics of the NMOS technology.
  * Perfect is the enemy of good enough.
  * As it stands, the design is reasonably hobbyist friendly, with 1
    complex SMD part to solder, but little else to cause issues. It also
    is probably cheap enough (as a completed unit) to fit people's
    discretionary budgets for this orphaned machine category.  Moving to
    a larger CPLD or adding in all of the components to better emulate
    the design will quickly overwhelm the costs and/or DIY nature of the
  * How much time do we really want to spend on this?  I guess that's a
    question to me to answer, and the answer is, not a ton more.  The B
    is a beast to leave open on the bench, the worldwide use for this
    design is probably measured in the tens, and at that level of
    interest, it's almost worthwhile to have 10 different design
    variants, one per use, instead of trying to make one design fit all
  * The beauty of open source (and this design is MIT based, which is
    extremely flexible, as some community members specifically asked for
    a more flexible license than GPL be used) is that the initial
    designer can work on the design until they are satisfied, while
    others can push the design even farther forward
  * I think your suggestion of holding the data bus at the same state
    through PHI low encourages people to design poorly.  The 6502 only
    guarantees data validity for 30nS past falling edge of PHI2
    (Tdhw:min = 30nS) Contemporary designs should assume a Tdhw <= 10nS,
    which is the latency on the CPLD I am using.  The 65C816S itself
    actually guarantees data to be valid on the data lines for 40nS past
    the falling clock, on speeds up to 2MHz.  In your use case, that
    means it was leaving data on the bus even longer than the NMOS
    6502's specs dictate.
  * Not trying to call your home built design capability into question,
    but I'm leery of addressing a concern only seen in a very limited
    and non-production set of circumstances.  There are so many
    unanswered questions.

I suppose, in the end, given the nature of the discussion, perhaps there 
should be "teams", like folks tend to categorize things into in social 
media.  Team "Exact" for those designs that are bug for bug compatible 
and timing perfect, and Team "Satisfactory" for those of us more 
pragmatic.  This might reduce conflict in the community.  We can brand 
devices like this and sd2iec as "Team Satisfactory" and perhaps folks 
won't expect perfection.  We can then steer the rest to other designs 
like 1541 Ultimate and Chameleon, when nothing but exact behavior will do.

Received on 2018-07-20 21:00:04

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