Den Tue, 17 Jul 2018 06:31:15 +0000 skrev "Baltissen, GJPAA (Ruud)" <ruud.baltissen@apg.nl>: > Hallo Jim, > > > > The system uses the E pin on the '816 to interpret setting the port > > pins: .... > > I really like that :) That would give me the 65816 I always liked to > have. It does mean that the Kernal has to be rewritten but I wouldn't > mind. > > May I politely point you to something? In the early days I equipped a > VIC-20 with a 65816 and an ISA expansion. After building the whole > thing I found out that I had misunderstood the behavior of the RDY > input. Negating RDY does stop the 65816 from performing any > instruction but does NOT stop it from outputting the content of the > bank register on to the data bus when E is (L). > > In time I found a solution by keeping the clock input (H) during the > time RDY was (L). You'll find the schematic at: > > http://baltissen.org/newhtm/65sc816.htm > > I hope this is some help. Good catch! Btw, how short random spikes on the CLK signal are allowed on a 65816? If RDY changes at almost the same moment that CLK input is going low, there might be a really short low spike on the CLK output, as the delay through the flip flop is slightly longer than the delay via IC2A+IC2B. That probably won't happen in a VIC, but still. -- (\_/) Copy the bunny to your mails to help (O.o) him achieve world domination. (> <) Come join the dark side. /_|_\ We have cookies.Received on 2018-07-17 21:00:04
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