Re: CBM-II Character Set and Colour Expansion (was: BASIC for the CBM-II/8088)

From: Mia Magnusson <mia_at_plea.se>
Date: Sun, 15 Jul 2018 21:59:19 +0200
Message-ID: <20180715215919.00007471@plea.se>
Den Sun, 15 Jul 2018 19:33:18 +0000 (UTC) skrev Steve Gray
<sjgray@rogers.com>:
> Add a 9th bit? How will that work? Sounds like it would add a lot of
> circuitry. Right now my mod gives you 256 different characters on
> screen, but sacrifices the reverse set. there is no way to do reverse
> unless we add some attribute memory. That's my next step. Attribute
> memory could be colour, font, blink, underline or some combination...
> whatever makes sense with 8 bits. On my ColourPET+G I have 4
> foreground + 4 background colours (RGBI digital), but I also have a
> mode where the 4 background bits are used to select 1 of 16 different
> fonts.for each character. For the 8088 card perhaps I could do 3 bits
> (8 colours) fg/bg and then 2 bits for blinking and something else.

I were thinking of a 9th bit of pixel data.

It seems like one half of a 74LS74 is used for the 9th pixel already,
and a signal called GRAPHICS from CA on the IEEE 488 handshake handling
6525 (U2) controls if the 9th pixel should be clear or repeat the 8th
pixel (D0) from the font rom.

By setting the GRAPHICS signal to always enable the 9th pixel (just
bend CA out of the socket on that triport, or do it in software), an
additional char rom with it's address lines in paralell to the
existing, could provide the 9th pixel data.

Adding attribute memory might require a duplication of the _VIDRAMWE_
circuit on page 2 of the schematics, using one half of a 74LS74 and and
one fourth of a 74S32 gate. Maybe parts of the _VIDRAMOE_ circuit also
needs to be duplicated, one sixth of a 74LS14, one fourth of a 74LS00
and one fourth of a 74S08 gate.

This circuit could probably be simplified.

Btw this begs me to actually find the time to make a timing diagram for
the B series. Even though the general operations are well known, we
don't have any timing diagram that shows the worst case of it's timing,
i.e. when all gates a signal is passing either are as slow as they are
allowed to be according to their spec, or the same but all gates are as
fast as allowed within their specs.

Page 2 of the B schematics combined with various other parts of the
schematics generates lots of signals that has to have the right timing.
This gives me the impression that the function is easy to understand
without a timing diagram, but hard to make hardware additions that's
guaranteed to actually work in all B machines.

-- 
(\_/) Copy the bunny to your mails to help
(O.o) him achieve world domination.
(> <) Come join the dark side.
/_|_\ We have cookies.
Received on 2018-07-15 22:01:34

Archive generated by hypermail 2.2.0.