On 7/10/2018 1:01 AM, Baltissen, GJPAA (Ruud) wrote: > > Hallo Jim, > > How is the development of the card going? > Phase I of development/design is done. Phase 2 requires I focus on REU functionality Phase 3 will allow the card an option to operate in parallel with the 6510 or operate as a replacement CPU for the 6510. Right now, I am learning the specifics of REU functionality (basically, being able to coordinate with VIC-II for the local bus to share memory. Specifically, one way or another I am going to implement a CPU accelerator for hte 64. Mostly to prove to myself I can do it. Right now, the big hurdle is sharing the 64 bus. I decided to implement REU functionality because it's a good place to learn, and I figured the outcome might be a working REU Verilog core. Writing data from 64 to external RAM is working fine, with the expected REU registers and such, but reading is not (for some reason, all 64 RAM locations get the value of the first external RAM location, and I can tell I am incrementing the counters). Once I can overcome that, then I can move to Phase 3a, which is running the 6808 as main CPU on 64 at 1MHz, and then Phase 3b would be to accelerate it and add in the code to halt the CPU if a memory value needs to be stored in main RAM. > The reason why I ask is that I finished the 6809 part of my assembler > yesterday. So if you need a tester, I could be of help. > I can share now, as an IPC mechanism (for parallel 6809 execution) is needed for operation. Are you aware of FLEX or OS/9 OS? JimReceived on 2018-07-10 20:00:04
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