Re: Weird /KERNAL line on old boards

On Sun, Jul 8, 2018 at 8:48 AM, Jim Brain <brain@jbrain.com> wrote:
> It's probably because the PLA combinatorial logic is not registered.  If one
> path is faster (or the inputs are faster), the output can cycle through some
> invalid states as the inputs settle.
>
> The larger PLA might register the outputs, not sure.

This explains  41ns sporadic selections. I simplified the code and
can't see full cycle selections any more. Maybe it was my mistake in
either coding or measuring.

Sharp PLA on 250469 boards indeed have clean /KERNAL selection line.

>
> I am just trying to think of a way you could overcome this.  I am wondering
> if you can use a specific address of KERNAL ROM as the trigger, like $ffff
>
> Jim

Previously I tried choosing specific addresses for triggering but it
didn't work. As you've wrote this I gave it a go again and this time I
chose a low address line (A4) mainly because my sid socket was empty
and had no easy access (my room is a mess) to higher address line.

Of course it didn't work :)  But then I thought why not choose the
triggering address with A4=0 and the code that modulates this (which
might just catch a sporadic Kernal selection) running through
addresses where A4 =1. That did indeed work :)

Overall I disable all roms off, I only enable it briefly*  where I
modulate the Kernal selection line. It becomes that unwanted selection
has A4=1, intended selection has A4=0. By the way, in this code there
is proof that accesses to processor port ($0001)  just don't drive the
address bus with that address. ( *not necessary though as long as code
running in addresses where A4=1)

May look gibberish on email but here is the code (damn pastie is
blocked in my country)


Regards,

Nejat

MODULATION_ADDRESS = $F000 ; A4 is low
;-- Complex Interface Adapter --
CIA_1_BASE = $DC00
CIA_2_BASE = $DD00

;-- CIA Registers --
CIA_INT_MASK = $0D

;-- Video Interface Controller --
VIC_CONTROL_1 = $D011
VIC_INT_CONTROL = $D01A
VIC_INT_ACK = $D019
VIC_BORDER_COLOR = $D020
VIC_SCREEN_COLOR = $D021

;-- Processor --
PROCESSOR_PORT = $01
PP_CONFIG_ALL_RAM = $34 ; RAM visible in $A000-$BFFF, $E000-$FFFF, $D000-$DFFF
PP_CONFIG_RAM_ON_ROM = $35 ; RAM visible in $A000-$BFFF, $E000-$FFFF
PP_CONFIG_RAM_ON_BASIC = $36 ; RAM visible in $A000-$BFFF
PP_CONFIG_DEFAULT = $37 ; $A000-$BFFF, $E000-$FFFF is ROM, default config.


*=$080E
SEI
CLD
JSR TurnOffInterrupts
JSR SwitchRamOnRom
JSR DisableDisplay
LOOP
LDX #$FF
-
DEX
BNE -
JSR Modulate
JMP LOOP

TurnOffInterrupts
ASL VIC_INT_ACK
LDA #$00
STA VIC_INT_CONTROL
LDA #$7f    ; $7f = %01111111
STA CIA_1_BASE + CIA_INT_MASK ; Turn off CIA 1 interrupts
STA CIA_2_BASE + CIA_INT_MASK ; Turn off CIA 2 interrupts
LDA CIA_1_BASE + CIA_INT_MASK ; cancel all CIA-IRQs in queue/unprocessed
LDA CIA_2_BASE + CIA_INT_MASK ; cancel all CIA-IRQs in queue/unprocessed
RTS

DisableDisplay
LDA VIC_CONTROL_1
AND #$EF
STA VIC_CONTROL_1
RTS

SwitchRamOnRom
LDA #PP_CONFIG_RAM_ON_ROM
STA PROCESSOR_PORT
RTS

*=$0910 ;A4 is high
Modulate
LDY #PP_CONFIG_RAM_ON_ROM
LDA #PP_CONFIG_DEFAULT
STA PROCESSOR_PORT
LDA MODULATION_ADDRESS
STY PROCESSOR_PORT
RTS