Quoting Jim Brain <brain@jbrain.com>: > On 3/3/2018 3:21 PM, Jim Brain wrote: >> A few more updates: >> >> I created v3 of the board. >> >> https://github.com/go4retro/Fake6509/blob/master/pcb/Fake6509_v3%20PCB.pdf >> https://github.com/go4retro/Fake6509/blob/master/pcb/Fake6509_v3%20PCB.png >> >> Changes include: >> >> * Relocate CPLD to other end of PCB, to address conflict with >> keyboard connector on B128. >> * Route data lines through CPLD to address bus contention during >> read of $0 or $1 >> * Add ground jumper on pin 1 to support NMOS 6502 and CMOS 65C02 >> >> If possible, I'd appreciate it if folks with 6509 systems could >> dload the PDF or PNG, print out, and verify mechanical placement. >> Please let me know if all is OK, so I can spin a new PCB. >> >> Jim >> > My apologies for the delay on this project. > > I was able to test the v3 board. NMOS 6502 seems to work fine (long > startup, function keys work), but I will run Michal's test app > tomorrow night. > > 65C02 does not work (it boots, but does not do long ram test). > Since the NMOS works fine, and the only thing different is the CPU > itself, I think the CMOS 65C02 uses fewer cycles to perform the > opcodes. Does anyone have a opcode cycle by cycle listing for the > 65C02 opcodes? > > Jim Hi, Jim. You'll find some details about timing *differences* in Table 7-1 of WDC's 65c02 datasheet [1], which makes a comparison with the NMOS 6502. On the 'C02 the $6C opcode (jmp indirect) takes one cycle longer. ADC and SBC also apparently take one cycle longer if you're in decimal mode. Table 7-1 makes a partially erroneous statement regarding "Read Modify Write Instructions absolute indexed in same page," claiming that these are all reduced from 7 cycles to 6. Most are (ROL ROR ASL LSR) but some aren't (INC DEC). Details here [2]. Jeff [1] http://westerndesigncenter.com/wdc/documentation/w65c02s.pdf [2] http://forum.6502.org/viewtopic.php?p=38895#p38895Received on 2018-06-28 16:00:06
Archive generated by hypermail 2.2.0.
