Re: DMA successes with Verilog

From: Jim Brain <brain_at_jbrain.com>
Date: Tue, 12 Jun 2018 13:31:41 -0500
Message-ID: <9b20973c-8779-e31e-41d4-f3957eda4448@jbrain.com>
> On June 12, 2018 at 11:12 AM Mia Magnusson <mia@plea.se 
> <mailto:mia@plea.se>> wrote:
>
>
>
> Nice!
>
> Seems like your expansion might be able to have a REU compatible mode
> in the future :)

Long in the future, perhaps.  I suspect that handling all of the 
functionality in an REU will thwart my efforts.

To add content worthy of this group:  Looking at the functionality of 
the REU, I noticed the "swap" functionality, and I wonder if one could 
perform 2 actions in 1 half PHI2 cycle.  I think the DRAM is 200nS or 
better, and maybe with that or with 150nS DRAM, a cart could place the 
address and set R/W to be a read for the first half of the high PHI2 
cycle, and then change to a write halfway through with new data on the 
data bus.  That would allow a swap to occur in half the time.  I am sure 
there's some reason why it won't work, but it seemed an idea worth 
considering.

Jim
Received on 2018-06-12 21:00:04

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