On 05/29/2018 06:02 PM, Francesco Messineo wrote: > On Tue, May 29, 2018 at 5:45 PM, Gerrit Heitsch > <gerrit@laosinh.s.bawue.de> wrote: >> On 05/29/2018 05:17 PM, Francesco Messineo wrote: >>> >>> On Tue, May 29, 2018 at 5:03 PM, Gerrit Heitsch >>> <gerrit@laosinh.s.bawue.de> wrote: >>>> >>>> On 05/28/2018 09:24 PM, Francesco Messineo wrote: >>>>> >>>>> >>>>> On Mon, May 28, 2018 at 8:51 PM, <silverdr@wfmh.org.pl> wrote: >>>>>> >>>>>> >>>>>> >>>>>>> On 2018-05-28, at 14:28, groepaz@gmx.net wrote: >>>>>>> >>>>>> >>>>>> >>>>>> Interesting. Due to VCO? And the original clock circuit with discrete >>>>>> elements? There was AFAIR also a kind of PLL involved. Do those exhibit >>>>>> the >>>>>> same problem? >>>>> >>>>> >>>>> >>>>> the original C64 clock generator circuit (is) a regular PLL (so, not >>>>> "a kind"), the reference divider circuit is inside the VIC-II IC which >>>>> is part of the PLL. >>>> >>>> >>>> >>>> But the design of the PLL on the old C64 is a bit on the dirty side when >>>> you >>>> look at the part of the circuit containing the 74LS193. >>> >>> >>> hm? >>> It's a typical design of the era, I've seen several PLLs where a >>> divider is made with a counter pre-loaded to a specific value and >>> counting either up or down with one bit being the output. I find also >>> clever using a half LS74 as a NOT port, since it was free anyway. >>> What do you consider dirty? >> >> >> Take a look at how it resets. They shorted 'carry out' with 'load' and added >> a 82pF capacitor to adjust the timing a bit. > > it "reloads" rather. Anyway, I knew you would point at that but it's > typical of that era really. > It works fine, that capacitor just lengthens a bit the reload pulse > due to asymmetrical sink vs source currents of the LS family. Well, yes, it works... But not really a nice way to do it. Also, have you looked at the output of the MC4044? I would have expected that signal to be less noisy. GerritReceived on 2018-05-29 19:00:20
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