Re: Reloaded Mk-II compatibility

From: Francesco Messineo <francesco.messineo_at_gmail.com>
Date: Mon, 28 May 2018 22:10:06 +0200
Message-ID: <CAESs-_y7NOXLs5u=1ua3pm6vmpvVi1PQH8uDQHs-zEHmgqJJ2Q@mail.gmail.com>
On Mon, May 28, 2018 at 10:04 PM,  <silverdr@wfmh.org.pl> wrote:
>
>> On 2018-05-28, at 21:24, Francesco Messineo <francesco.messineo@gmail.com> wrote:
>>
>>> Interesting. Due to VCO? And the original clock circuit with discrete elements? There was AFAIR also a kind of PLL involved. Do those exhibit the same problem?
>>
>> the original C64 clock generator circuit (is) a regular PLL (so, not
>> "a kind")
>
> "A kind" was in the meaning of "one of possible kinds", not in the meaning of "exotic" or so.
>
>> the reference divider circuit is inside the VIC-II IC which
>> is part of the PLL.
>> The MOS8701 is a divider/digital delay synthesizer and doesn't use the
>> VIC-II divider (but the divider it's still needed to generate the
>> 6510's clock).
>> Just for the record.
>
> Right, what I am interested in is whether the C64s with the original clock generator circuit (the regular PLL/VCO) exhibit the same problem with said peripherals as the "Reloaded" (and - as gpz says - the newer boards equipped with the 8701 replacement). If that's the case, then it is hard to argue that it is a compatibility issue on the "Reloaded" side. One could even say that "Reloaded" is more compatible with the original design... ;-)

agreed, but no clock generation circuit should suffer from power
spikes, supply bypassing should be carefully planned too when
designing something.

F
Received on 2018-05-28 23:01:43

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