> The CBM CMOS chip I'm working on the spec sheet in a few gates mentions "GATING" inputs and outputs, what does this mean exactly? > To have a true synchronous counter, only one common clock is used in all stages. So to keep the upper stages from counting at the wrong count, say instead of counting every one clock to say every 10 counts, you would use gating signals like 'count enable' inputs and 'ripple carry' outputs in your design to keep things counting properly and on one common clock. This is considered a better design rather than simple 'ripple counters' that uses an output from the previous stage to clock the next stage. That method will accumulate propagation delays and can cause glitches, etc in the overall logic circuit. -- Sent from: http://cbm-hackers.2304266.n4.nabble.com/Received on 2018-05-22 00:00:07
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