On 5/7/2018 2:56 PM, smf wrote: > I believe.... > > Writes to PCR registers are the same format as the CR register, you > write to them but mapping doesn't change until... > > Writes to LCR register tells it to load from the corresponding PCR > register into the CR register. It's so you can quickly switch between > banks without having to keep calculating the CR register or passing it > around. Yep, got it. > > So PCRA can be the CR for where code is, PCRB could be the CR for > where the kernal reads/writes from. The kernal then only needs to know > to hit LCRB, perform the access and hit LCRA. I am keenly interested in MMU design, since I am working on one for another platform. It looks like, even with the weird address sharing of A&/A6 and A5/A4, there are 3 additional 16 byte windows in $d5xx that could be used to extend the system. I'd favor an approach like the TANDY Color computer, that splits the 64kB into "pages" that can reside in 512kB of memory. IN the Coco MMU, the system uses 8 6-bit values to denote the "bank" value for each 8kB slice of main memory, and then they offer a "task" register that can quickly flip between a complete set of mappings. I'd recommend using 4kB pages, using one $d50x register to hold the "task" number, and using 16 of the free registers to hold 16 "page" registers, 1 for each 4kB page At 8bits, that'd be able to manage 1MB, while extending the MMU regs to 13 bits would allow 32MB of mapping. With a task register, you could have 256 mappings. The additional 3 bits could be used for "IRQ on write, mark RAM as read-only, and reserved. JimReceived on 2018-05-08 03:00:02
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