> On 2018-03-16, at 22:17, And Fachat <afachat@gmx.de> wrote: > >> So not on the rising edge but "while". How long / far after the rising edge then? Are there any guidelines for that? Putting aside how to do it correctly in VHDL, because that's another subject. > > Usually you would let the address lines go through your internal select logic and provide the data on the bus once it's there for reads. I don't/won't have much select logic inside. I only have two address lines. The rest is decoded externally. Do you think that'd be enough? > Make sure reads have no side effect like clearing the interrupt as on the 6526 that is stupidly broken in that respect. Then it does not matter if address lines change during reads, you just provide the data from the different location shortly after the address change. OK, so I understand that it won't matter that much if the addresses and therefore output change as long as reads have no side-effects, like clearing/setting something on the way. What about enabling outputs. Any other, particular consideration here? > For writes, handle the select logic like on read and pass the select signal up until the input latch. Then use the falling edge of phi2 to take in the data. To avoid bus contention disable outputs when r/w is low. > > This even handles the case where r/w changes from read to write in the middle of the cycle. Before the change you put out the data read, after the change you disable the outputs and wait for phi2 going low. > > The tricky part is when r/w goes from low to high during the cycle while phi2 is high. Because usually the input latches are clocked by the > > clk = select AND write AND phi2 > > If r/w goes to read during the cycle, clk suddenly changes and data is latched where it shouldn't. This does not happen on the C64 where the VIC only reads, so no problem here but maybe in other setups. > > If you need to handle this case you need to delay the rising edge of phi2 (but of course not the falling edge) until address and r/w are stable. Well, the problem with delays is that I don't know a way to do it in VHDL without having additional, faster clock, which I don't have. So I'd need to have some form of a buffer and do it externally. > Hope this helps > André It does. Thanks a lot. -- SD! - http://e4aws.silverdr.com/Received on 2018-03-18 19:00:02
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