Re: Building a 6502 peripheral - timing

From: And Fachat <afachat_at_gmx.de>
Date: Sat, 17 Mar 2018 08:55:29 +0100
Message-ID: <16232f4d180.27e0.b4d1f2b66006003a6acd9b1a7b71c3b1@gmx.de>
Am 17. März 2018 00:04:50 schrieb Mia Magnusson <mia@plea.se>:

Den Fri, 16 Mar 2018 07:50:13 +0100 skrev And Fachat <afachat@gmx.de>:
Also, with " take the address during phi2 high " is critical like in
the c64, as the address line may still change at the beginning of the
cycle. So if you have IO here that e.g. clears the interrupt when
reading the interrupt register, that may accidentally trigger here.

It seems like that kind of stuff should ideally be triggered by the
falling edge of PHI2.

It should not at all be triggered by a read considering the reads of 
"unwanted" addresses when the NMOS 6502 calculates indexed addressing modes.

Also you don't want to clear interrupts by reading in a more modern 
operating system where you link together drivers for peripherals that do 
not know of each other.... For the 6526 IRQ you have to basically use a 
shadow register in RAM for that to not loose interrupts. A nuisance....

André

André

--
(\_/) Copy the bunny to your mails to help
(O.o) him achieve world domination.
(> <) Come join the dark side.
/_|_\ We have cookies.
Received on 2018-03-17 09:00:02

Archive generated by hypermail 2.2.0.