Re: Building a 6502 peripheral - timing

From: Mia Magnusson <mia_at_plea.se>
Date: Sat, 17 Mar 2018 00:03:05 +0100
Message-ID: <20180317000305.00005316@plea.se>
Den Fri, 16 Mar 2018 16:59:38 +0100 skrev silverdr@wfmh.org.pl:
> > On writes take the addresd line while phi2 is high and take the
> > data from the bus at the falling edge.
> 
> Doesn't it imply race condition? I mean if I stop driving the bus on
> the falling edge, and CPU tries to read it at that very edge? Or is
> it somehow "guaranteed" that CPU will take the data before PHI2
> starts to fall?

The timing sheets for the CPU should give you information on for how
long time the data bus must still be stable after PHI2 falls. 



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Received on 2018-03-17 01:00:02

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