Re: Building a 6502 peripheral - timing

From: Gerrit Heitsch <gerrit_at_laosinh.s.bawue.de>
Date: Thu, 15 Mar 2018 18:33:50 +0100
Message-ID: <3a7a5018-8ce6-5025-cc5e-c92564e962ae@laosinh.s.bawue.de>
On 03/15/2018 05:52 PM, Mia Magnusson wrote:
> Den Thu, 15 Mar 2018 09:49:43 +0100 skrev Gerrit Heitsch
> <gerrit@laosinh.s.bawue.de>:
>> On 03/15/2018 09:21 AM, Baltissen, GJPAA (Ruud) wrote:
>>> Hallo Patryk,
>>>
>>>
>>>> No, it can't. PHI2 is nowhere to connect to there so it has to be
>>>> taken care of externally.
>>>
>>> I meant: the moment you disable CS, the state of WE doesn't matter
>>> anymore. In my designs I always make sure that PHI2 is part of CS
>>> selection circuit. Using R/W could be dangerous: what if WE becomes
>>> (H) before CS? In that case a bus clash can occur, even it is just
>>> a very short time.
>>
>> In most systems you have bus clashes, but yes, short ones. Someone
>> said that this is the reason why a 7501 uses less power than a 8501
>> (20mA less from, what I measured). The 8501 is faster, so it gets its
>> lines active before the other side becomes inactive.
> 
> The most important thing here is to study the data sheets /
> specifications for the involved ICs to make sure that there is no harm
> when a short bush clash occurs.

With NMOS-drivers on both sides there can be no harm, that comes from 
the way NMOS and HMOS works.


> You don't explicitly need to have a short bus clash for a fast bus to
> work, it's just that it were probably easier to implement back in the
> days.

Back then the timing could change between different batches of the same 
chip...

  Gerrit
Received on 2018-03-15 19:06:11

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