Building a 6502 peripheral - timing

On the wave of the recent 6509 / 6502 discussion... when building or connecting a peripheral that would allow both reading and writing, what is basically needed are the following signals:

* _CS (from address decoder)
* R_W (from 6502)
* D[0..7]
* possibly some low address bus lines A[0..3] for example
* some chips take PHI2

http://archive.6502.org/datasheets/mos_6500_mpu_nov_1985.pdf

shows timing diagrams. I wonder what would be the required timing for a peripheral without PHI2 clock input. I suspect something similar to what SRAM chips specify. Any hints as where to put attention? Like relations between _CS, R_W, ... ?

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