Re: Hardware emulation of 6509 using 6502?

From: Dr Jefyll <laughton_at_cyg.net>
Date: Tue, 13 Mar 2018 15:55:08 -0700 (MST)
Message-ID: <1520981708878-0.post@n4.nabble.com>
Jim Brain wrote
> Changes include:
> 
>   * Route data lines through CPLD to address bus contention during read
>     of $0 or $1

http://cbm-hackers.2304266.n4.nabble.com/Hardware-emulation-of-6509-using-6502-td4664265i200.html

 Hello, Jim and all.  This new routing of the data bus matches how a 65816
is usually set up -- using a bus transceiver, I mean.  And that gave me a
rather interesting idea.  What you've done makes the board almost ready to
accept a 65816 -- I'm serious!  Most of the changes would be just a matter
of CPLD programming. 

 Okay, lots of questions, and here are (some of) the answers.  Comments
welcome from everyone.  I'm talking about an interposer board very much like
what we've got already -- in other words, a 6509-less 6509.  And the revised
board  could still fulfill the 6509 role.  But instead of relying on a 6502
it'd use a 65816, operating by default in "Emulation Mode." (Yes, the '816
can emulate a 6502.)

 A new WDC '816 is hardly any more expensive than a new WDC 'C02, so cost
isn't a barrier.  Also the pinouts are similar enough not to present a
problem.  But this board could, using the XCE instruction, freely go from
Emulation Mode to Native Mode and back again.  

 Native Mode makes available a far more powerful processor, with enticing
options such as 16-bit accumulator and index registers.  But an even greater
benefit, IMO, is bypassing the tragic and crazy-making limitations
associated with the 6509 Execution and Indirect registers.  Except for the
time spent in Emulation Mode the CPLD would cause those registers to
disappear, cued by the very convenient E (Emulation Mode) output pin on the
'816.

 Instead, the high address bits sent to the motherboard as "P3-P0" would
come from the '816.  The '816 outputs high address bits on its data bus pins
during Phase 1, and the CPLD could easily include the address latch required
to capture these bits.  And the E pin could tell the CPLD whether to use
6509 bits or 816 bits as P3-P0.  

In Native Mode the '816 would see all sixteen 64K banks as a single,
/contiguous/ space. Arrays and other data structures could even straddle
bank boundaries.  And long (alternate bank) subroutine calls would be
trivial rather than torturous.

 Potential problems include undocumented NMOS 6502 opcodes, which the '816
doesn't support.  (But neither does the 'C02.)  Interrupts might require
attention, but it's doable.  No special action is required as long as both
the foreground task and the ISR use Emulation Mode.  (And at reset the '816
automatically wakes up in Emulation Mode.)  But when modes get mixed you'd
need to use the double set of interrupt vectors provided for this purpose.  

 Is anybody interested in this?  And can we convince Jim to try building
it?? ;o)

 -- Jeff




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Received on 2018-03-14 22:45:48

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