Re: Something else... 8501 GATE-IN

When display=off TED only uses the bus for the DRAM refresh. That is why it 
switches back to single clock.
Although it seems to be a waste of time when using SRAMs I believe we should 
not worry because of this. What could we win with those extra 5 CPU cycles 
per scanline? Comparing to today's fast CPUs its nothing.

Istvan

-----Original Message----- 
From: Mia Magnusson
Sent: Wednesday, March 14, 2018 5:51 PM
To: cbm-hackers@musoftware.de
Subject: Re: Something else... 8501 GATE-IN

Den Tue, 13 Mar 2018 16:49:11 +0100 skrev Gerrit Heitsch
<gerrit@laosinh.s.bawue.de>:
> 6) When set to display=off, TED runs the CPU at double speed all the
> time (AEC constantly HIGH), except for 5 consecutive refresh cycles
> each scan line. With my C16 converted to SRAM (*), too bad this
> cannot be disabled. :)

Well, if you add hardware to disconnect TED from RAM you could make a
circuit that syncs on hsync (I guess you'd need a sync separator for
that) and counts clock cycles and disconnects TED from RAM and forces
AEC high during those 5 cycles. :)

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