Yes, great work, Jim! *Very* pleased to hear this news! Jim Brain wrote > * I don't know that anything special is needed on the PHI2 signal. Well, early indications are you're right! And, y'know, if a modern WDC 65C02 were to be used then the delay from clock input to clock output is gonna be pretty darn small anyway. These are *really* fast parts, after all. > * I simplified the Verilog (and Dr. Jefyll's schematic by performing > the combinatorial logic on the DATA and SYNC inputs before storing > into the flip/flop. This reduces the number of flops (macrocells) > needed by 7. NOt terribly useful, since there's plenty of space, > but it's more compact. Again, this is probably acceptable. My original schematic purposely does things "the hard way" in order to allow more headroom for speed. You wanna take pains not to increase the data-hold time required at the end of each cycle. And the way to do that is to capture the byte first, then decode it later (after the cycle has ended). You changed it around so the decoding happens before the cycle ends and /then/ the result is captured -- and apparently the CPLD is fast enough to make that option satisfactory (for that particular computer). Who know, though -- it's fun to speculate. Maybe someday someone will take things to a whole other level and create a 20 Mhz 6509! In that case it'll be worth considering a switch back to my original logic -- capture first, decode later I mean. Congratulations again on your efforts -- it's great to see the rubber hit the road at last, and kudos to you for getting serious and taking up the challenge! -- Jeff -- Sent from: http://cbm-hackers.2304266.n4.nabble.com/ Message was sent through the cbm-hackers mailing listReceived on 2018-03-01 07:00:02
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