Re: Hardware emulation of 6509 using 6502?

Den Sun, 25 Feb 2018 15:09:32 -0700 (MST) skrev Dr Jefyll
<laughton@cyg.net>:
> Jim Brain wrote
> > I don't think so.  6509 requires external clocks, but the 652 uses
> > an internal clock generator.
> 
> I'd forgotten that -- sorry.  What you did was worth a try.  Tidy,
> too.
> 
> Again I'll suggest an UN-tidy solution, a temporary one at least.
> Using a flying lead, is there a point on the motherboard that's a
> slightly earlier version of what gets applied to the Phi2 input (pin
> 40) of the 6509?  If so, it could drive the 6502's Phi2 input (pin
> 37).

Check page 1 and 2 of the schematics.

On page 2 there is a 74S299 which is a shift register with all sorts of
bells and whistles, but it is only used as a serial in parallell out
shift register. Compined with a 74LS30 8-input NAND gate it is fed a 1
each time all outputs are 0, otherwise it's fed a 0. In practice this
acts as a ring counter. I'm not sure if it has 8 or 9 stages, but as
the master clock is 18 and not 16 MHz I assume this actually has 9
stages. (18/9=2MHz).

("phi" in the following text refers to a 0 with a / drawn through it).

Continuing on page2, QC of the 74S299 feeds PR (=SET) of U57, a 74S74,
while QG of the 74S299 and the DOT CLOCK (which feeds the 74S299) feeds
CLR (RESET) of the 74S74. The Q and _Q outputs of this 74S74 generates
the signals called Qphi2 and _Qphi2_.

I assume this generates a perfectly symmetrical clock with 4 and a half
18Mhz clock pulse on each half of the 2MHz CPU clock.

Moving to page 1, Qphi2 and _Qphi2_ feeds two sets of flip flops
manually buildt from the simple NOR gates in a 7428 (not a LS, L or S
piece). One of the two flip flops have 180 ohm pullup resistors and
then feeds phi1 and phi2 to the 6509. The second of the two flip flops
generates two signals called Sphi1 and Sphi2, which seems to feed
varios parts.

The 7428 seems to be an uncommon part. The datasheet I found has some
Asian characters that I can't read but as I understand it a standard
gate has a delay of 9nS when the output goes high and 12nS when the
output goes low. Assuming a perfectly symmetrical signal from the 74S74
there would be a 3nS difference between phi1 and phi2 feeding the CPU.

The 74S299 on page 2 has an enable circuit which is fed by a signal
called PIP1 which has a 1k resistor pullup, and which also enables the
buffers U62 and U63 on the upper part of page 1.

I'm not sure what PUP1 is supposed to be used for. I can't see it being
driven by anything. Maybe it's some kind of leftover from an early
attempt at the P500 (the B series machine with VIC-II instead of 80
column character video), or some other mechanism for stalling the cpu.

Anyway it seems like there are plenty of different clocks available. By
combining the outputs of the 74S299 with the master clock it's possible
to sync anything to the cpu clock with 36 precise steps.

Jim: Is your logic analyzer fast enough to trigger on both edges of the
18MHz clock? If so it would be really nice if you could use it to make
some kind of timing diagram of the actual signals involved. This could
of course also be done with any reasonable oscilloscope. (I would do
this if I had a B/CBM-II machine myself).

There are more stuff involved with the timing, but this is what seems
to generate the CPU clocks.

If it's ever going to be possible to actually make my idea of a replica
a reality, we probably need to make a complete timing chart of more or
less everything in the machine. Although an exact replica would be
nice, I'd prefer if it's built by the same kind of technology used back
in the days but with parts that's not hard to source. (I guess that
standard TTL, S TTL (not LS) and uncommon types as 74S299 and 7428,
might be hard to source and it actually seems like a good idea to
replace the timing generation circuit by something else.


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