> because the 6502 fails every write, instead of the correct value, it > puts on the databus the previous value read from the databus itself. I can't help thinking this is the result of the LA taking its sample on the *rising* edge of Phi2. Frankly, I would expect *both* chips to appear faulty with this setup. But I hear what Jim's saying -- there should be one clock setting on the LA that works for both chips. Have you tried using the falling edge of Phi0 as the LA trigger? I have no explanation why falling edge of Phi2 isn't successful in all circumstances. But Phi0 is almost the same signal, just time-shifted slightly. J :o) Quoting Francesco Messineo <francesco.messineo@gmail.com>: > On Sun, Feb 25, 2018 at 9:46 PM, Micha? Pleban <lists@michau.name> wrote: >> Hello! >> >> Jim Brain wrote: >> >>> The system goes along fine until the CMP $03fa at $f99e. The 6509 reads >>> $f0, while the 6502 reads $f8. >> >> This is not a problem. The CPU is reading from uninitalized RAM here, so >> a random value is being read and that's OK. AFAIR, this is a memory >> location containing the "warm start" flag; after initialization, a magic >> value is written there. >> >>> After a bit, the paths greatly diverge. >>> I think I am out of my element, and need help to move beyond this. >> >> The real problem is at $F9B9: LDA $97. The code earlier expects the >> value $00 that it has written there, and 6509 indeed reads this value >> back, whereas 6502 reads $97. Therefore the following BMI instruction >> branches back. > > because the 6502 fails every write, instead of the correct value, it > puts on the databus the previous value read from the databus itself. > I'm not sure why, I don't know what hardware is in the middle between > 6502 and the actual data bus. > > > F > > Message was sent through the cbm-hackers mailing list Message was sent through the cbm-hackers mailing listReceived on 2018-02-26 00:00:02
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