Re: Hardware emulation of 6509 using 6502?

From: Michał Pleban <*lists_at_michau.name*> Date: Sun, 25 Feb 2018 22:36:42 +0100 Message-ID: <5A932C6A.2090403@michau.name> · lists_at_michau.name

Hello!

Jim Brain wrote:

> Scope trace shows a delay of ~17nS

If the clock is at 2 MHz, then half a clock cycle is 250 nS, therefore
17 nS is 1/15 th of the cycle, correct?

I can imagine a 32 MHz crystal and a 4-bit counter in the CPLD which is
synchronized with the incoming PHI2 but generates PHI0 for the 6502
which is shifted back 1/16 th of cycle.

Regards,
Michau.

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