Re: Hardware emulation of 6509 using 6502?

From: And Fachat <afachat_at_gmx.de>
Date: Sun, 25 Feb 2018 08:58:16 +0100
Message-ID: <161cbf831c0.27e0.b4d1f2b66006003a6acd9b1a7b71c3b1@gmx.de>
Am 25. Februar 2018 05:59:00 schrieb Jim Brain <brain@jbrain.com>:

> On 2/24/2018 9:19 PM, Dr Jefyll wrote:
>> Dr Jefyll wrote
>>> We can't have
>>> read data from memory at $0000 or $0001 /also/ attempting to drive the
>>> bus.
>> Huh -- or maybe we CAN!  The question is, are /writes/ to $0000 and $0001
>> also passed on to RAM? With the present arrangement I think they are. That
>> means it's OK to have two bus masters later when the read occurs, because
>> the data will be the same!
> I was going to response earlier.  I don't think it is a problem.
>
> If there is no RAM at 0/1, then the CPLD owns the bus.
> If there is RAM at 0/1, then the CPLD and the RAM will both own the bus,
> but there will be not a major problem,
>
> The only issue is if there is ROM at 0/1
>>
>> But is the present arrangement acceptable? I heard some discussion somewhere
>> about writes to $0000 and $0001 /not/ being passed on to RAM. Is that a
>> desirable thing? Here's where my lack of CBM knowledge becomes apparent...
> This is an issue with the 6510, where the parts are truly internal, and
> no external write is asserted

But as we have banks of memory, would the memory not contain the last write 
_in this bank_? So if I write the register to move to another bank, the new 
bank number is written in the old bank memory location.

So there could be a conflict when reading in the new bank, because the new 
bank memory location has the last write from leaving it, while the cpld has 
the current bank.

Right?

André



       Message was sent through the cbm-hackers mailing list
Received on 2018-02-25 09:00:43

Archive generated by hypermail 2.2.0.