Jim Brain wrote > On 2/20/2018 3:11 PM, Mia Magnusson wrote: >> > https://github.com/go4retro/Fake6509 > > Initial Verilog is there. As always, comments welcome and appreciated. > > Jim > > -- > Jim Brain > brain@ > www.jbrain.com The Verilog looks good, I'd say. Not that I'm an expert! But it set me thinking about something not discussed in my 6502.org post -- namely, the ports at $0000 and $0001. Simple stuff, right? But there's a problem. When the CPU reads the Indirect or Execution register, there needs to be some way to let that register take exclusive control of the data bus. We can't have read data from memory at $0000 or $0001 /also/ attempting to drive the bus. I can think of two ways to fix this. The tidy way is to include a '245 bus transceiver as part of the adapter board. (Or let the CPLD perform the transceiver function.) The transceiver function would be told when to tri-state by the CPLD -- ie, when a read of the Indirect or Execution register occurs. The un-tidy way is to take that same signal from the CPLD (the tri-state signal, I mean) and run a flying lead to logic on the motherboard, attached in whatever way causes the data bus to float. Example: tie onto an unused input on the memory decoder. -- Sent from: http://cbm-hackers.2304266.n4.nabble.com/ Message was sent through the cbm-hackers mailing listReceived on 2018-02-25 04:00:03
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