Re: Hardware emulation of 6509 using 6502?

From: Michał Pleban <lists_at_michau.name>
Date: Thu, 22 Feb 2018 12:57:28 +0100
Message-ID: <5A8EB028.7050901@michau.name>
Hello!

Jim Brain wrote:

> * The XOR gate protects against the false opcode fetch that occurs
> whenever an interrupt is recognized. There's a risk that a $91 or $B1
> opcode will get fetched but not executed. If this happens the circuit
> mustn't respond. To recognize the beginning of the cpu's interrupt
> sequence we look for the unique circumstance of the address bus failing
> to increment in the cycle following an opcode fetch. No increment means
> the least-significant address line, A0, will fail to toggle. The output
> of the XOR gate will be low, thus inhibiting the circuit.

OK, that makes sense.

Otherwise, I don't see anything obviously problematic with the Verilog
code. Do you have any idea what still needs to be finished there?

Regards,
Michau.


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Received on 2018-02-22 12:03:37

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