On 01/05/2018 01:36 PM, Francesco Messineo wrote: > On Thu, Jan 4, 2018 at 7:19 PM, Francesco Messineo > <francesco.messineo@gmail.com> wrote: >> On Thu, Jan 4, 2018 at 7:09 PM, Gerrit Heitsch >> <gerrit@laosinh.s.bawue.de> wrote: >>> On 01/04/2018 06:56 PM, Francesco Messineo wrote: >>>> >>>> Hi all, >>>> as I'm repairing a 2001 320008 assy, I'm trying to test the 6550s and >>>> 6540s on a microcontroller board that I've made. >>>> I would use a real 6502, but I've only one spare left, so that's not >>>> an option :) >>>> >>>> It seems that the 6550 latches the selects, address and R/W line (for >>>> example lowering R/W after PHI2 L->H always results in a read cycle) >>>> on the rising edge of PHI2, but still I can't make a correct read or >>>> write cycle. >>> >>> >>> How much time before the rising edge of PHI2 did you set up the address >>> lines? There might be a minimum (and maybe maximum...) setup time for the >>> address lines before PHI2 can go high. > > one question: would you setup data bus before PHI2 rising edge on a write cycle? > Currently I'm outputting the data after the PHI2 rising edge, they are > stable at the PHI2 falling edge anyway. I'd look at the timing diagram for the 6502 write cycle and try to replicate it as close as possible. Onky change the timing once you get successful reads and writes. Gerrit Message was sent through the cbm-hackers mailing listReceived on 2018-01-05 15:00:02
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