On Fri, Dec 29, 2017 at 1:50 AM, Mia Magnusson <mia@plea.se> wrote: > Den Thu, 28 Dec 2017 15:44:13 +0100 skrev Francesco Messineo > <francesco.messineo@gmail.com>: >> > I don't have any idea why the 6540 needs the latch. An EPROM >> > doesn't need one. >> >> it probably doesn't *need* a latch, they thought it would be useful in >> some other architectures, before deciding it would be cheaper to add >> more glue logic and use standard RAM/ROMs. >> >> If the 6540 latches addresses internally on rising edge of PHI2 it >> means it can't easily be read on a standard programmer. > > Well, a standard eprom programmer would read the old adress when > A0/PHI2 is low, and when A0/PHI2 goes high the 6540 would output > correct content on the data bus. Thus you'll have to throw away every > odd byte from the readout, but every even byte would be fine. This > assumes that there are no noise on A1...Ax at the time A0 goes high. > It's not that easy: if you use the plain A0 as phi2, then A0 toggles together with other addresses, it means that the rising edge of A0 is too close to the other addresses edges, and that violates the Tads of 80 ns minimum required by the 6540 (it means that the last changing address and select signal must change 80 ns earlier than the phi2 raising edge). So, to use a standard programmer for a 6540 it must either be that this programmer issues any of /OE or /CE after setting the address bus and we invert this signal and use it as PHI2, or we delay A0 at least 80 ns and feed it to PHI2 and then discard half the bytes read. This last solution also works only if the particular programmer we want to use doesn't check for tristate data bus during reads (a couple of the ones I have, do check for tristate and abort reading if the device doesn't drive the data bus). Frank Message was sent through the cbm-hackers mailing listReceived on 2017-12-29 10:00:02
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