On Thu, Dec 28, 2017 at 12:36 PM, Gerrit Heitsch <gerrit@laosinh.s.bawue.de> wrote: >>>> That's what I think too. I'll discover it in a few days anyway :) >>> >>> >>> >>> If it doesn't, try inverting A0 before feeding it into the clock input. >> >> >> hm? Why should it matter, other than for adding a delay? > > > It depends on how the prommer sets up the address lines and if there is a > address latch inside the ROM involved. > > I have a few SRAMs that are 2114 compatible, but use /CS to latch the > addresses internally. You cannot use them as color RAM in a C64 unless you > OR the /CS signal with /RAS. It could be. The only edge of phi2 that can latch stable addresses and selects is obviously the rising edge, and according to this page: http://www.amiga-stuff.com/hardware/6540.html the 6540 needs 80 ns as address setup time before phi2 positive edge. So, if it's latching addresses (as it seems now the case), then A0 can't work as phi2 clock since it would not meet the Tads, it could be used as phi2 if it's externally delayed by at least 80 ns and the read cycle of the programmer is slow enough to allow this additional delay before data bus is sampled. Now, my question is, how the various 6540 to 2716 work? I haven't seen a schematic where this phi2 latching action is actually exploited, everyone's using a simple '138 to decode all the CS and phi2 into a single /CE for the EPROM (including me with my own adapter, but I've never tested it so far). If they indeed work with a simple '138 decoder and no latch, then it means that the address bus is stable during the high phi2 phase anyway. Did anyone test if the 6550 RAM does the same latching on phi2 raising edge? I'll discover it soon too, but maybe someone already knows. Frank Message was sent through the cbm-hackers mailing listReceived on 2017-12-28 13:00:02
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