On 11/24/2017 07:00 PM, Francesco Messineo wrote: > Hi all, > I'm going to repair a PET 2001, the board with 6540 ROMs and 6550 RAMs. > I'm still in the phase of studying the schematics to understand this > particular design. > Now, I'm not really getting why the R/W signal to all the RAMs, > including the two video RAMs is ANDed with the /SELE signal, can > anyone shed some light here? /SELE? If that means PHI2, then it's just what you usually need to do in a 6502 system. R/W can only gow LOW, meaning a write cycle, as long as PHI2 is HIGH. If you don't do it this way, you will corrupt the data in RAM. > On the 2001N board, the RAM R/W signal is just the CPU's signal plus > one buffer and two inversions. Those are DRAMs if I'm right. They don't care about R/W as soon as /RAS goes HIGH. Gerrit Message was sent through the cbm-hackers mailing listReceived on 2017-11-24 19:02:30
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