Am 13. November 2017 19:49:03 schrieb Francesco Messineo <francesco.messineo@gmail.com>: > On Mon, Nov 13, 2017 at 7:37 PM, Mike Stein <mhs.stein@gmail.com> wrote: >> >> --- >> Some drives use 2332s with an active-high chip enable and it looks like >> that's the case with the 2/3/4040 drives' CS2, so you might also have to >> add an inverter in order to use 2532s. > > > right.... clock phi2 from the 6502 (buffered) goes to pin21 of all the > ROMs. It prevents the ROMs to be selected during the low part of phi2. > Now I'm puzzled, what would drive the data bus during the low part of > phi2 that they had to prevent a possible bus conflict? The drives have two CPUs that run 180 degrees out of phase, i.e. one CPUs Phi2 is the others phi1 and vice versa. The databusses of both CPUs are directly connected, so using Phi2 to disable ROMs for the DOS CPU when the FDC CPU is active makes totally sense. André Message was sent through the cbm-hackers mailing listReceived on 2017-11-13 20:01:58
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