Am 8. November 2017 4:41:23 PM schrieb Mia Magnusson <mia@plea.se>: > Den Tue, 7 Nov 2017 19:19:44 +0000 (UTC) skrev Steve Gray > <sjgray@rogers.com>: > > It's interesting that the 8296 has two banks of 64k, but has the data > bus in parallell and reads two bytes for the graphics between each cpu > memory access. See details about the 8296 crtc integration here. http://www.6502.org/users/andre/petindex/crtc.html#8296 Memory is accessed in 4MHz and does 2 consecutive reads in the CPU's Phi1 part of the cycle to accommodate for the 80 column display. André Message was sent through the cbm-hackers mailing listReceived on 2017-11-09 06:00:02
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