> On 2017-11-06, at 16:58, Mia Magnusson <mia@plea.se> wrote: > >> It is essentially what I described a while back for making c64 output >> a valid pal/ntsc signal while maintaining perfect sync between the >> cpu/sid & vic, by speeding up/slowing down the system clock to make >> the sync pulses hit at the correct time. >> >> I wasn't considering syncing to an external sync, which would add >> some complexity. But it would be an awesome project. > > If you want a signal that has correct interlace you cannot do this > without breaking sampled audio playback, as you have to halt the VIC > chip for one line to insert the interlace line. AFAIR The idea was to slow down/speed-up the clock so that no halting would be necessary. > The only way to avoid > this is to have a buffer for video signal that can hold up to one line, which was my idea from the very beginning.. > and run the VIC so the v-sync is perfectly aligned but H-sync slightly > off so it will drift exactly one line until that extra blank line is > needed... ... and generate the proper pulse sequence for odd/even field. -- SD! - http://e4aws.silverdr.com/ Message was sent through the cbm-hackers mailing listReceived on 2017-11-06 19:02:32
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