Re: Handic VIC-Switch

Den Wed, 1 Nov 2017 12:56:06 -0500 skrev Jim Brain <brain@jbrain.com>:
> On 11/1/2017 10:17 AM, Mia Magnusson wrote:
> > Will a computer send this FF command even when the VIC-Switch pulls
> > DAT low?
> I doubt it, they chose it in no small part because *NOTHING* is
> supposed to happen before ATN going low.

It seems like this is something worth investigating.

> > Is anything else than FF ever sent before ATN? If not, then the
> > switch just needs to remember if burst mode were requested or not,
> > and send FF to the device before connecting it to the computer.
> > This assumes that the computer can handle the delay.
> I agree, but your "just" hides a ton of complexity.

Is there really more than sending 8 clock pulses and drive the data
line? Of course with the correct polarity of all stuff e.t.c.

8 pulses could for example be generated by a 4-bit counter and one half
of av 7474. An external signal triggers the 7474, one of it's outputs
releases the reset line of the counter and when 8 pulese have been sent
the fourth bit of the counter goes active and that makes the 7474
switch state again. The state of this 7474 can also drive the data
line. (Care must be taken if both S and R of the 7474 are used - if
both become active at the same time then both Q and _Q have the same
logic level IIRC). Maybe some more logic is needed to make a correct
delay between this "burst initiation" signal and connecting the drive
to the computer. Perhaps it's easiest to use a 4-bit counter with
decimal mode to have 2 clock pulses that's not transmitted but used for
timing purposes within the unit. Then we might not even need the 7474,
it could all be a state machine where a gate inhibits the clock signal
if the counter is at 8 or 9 and it isn't receiving a start condition.

P.S. as (I assume) this would anyway require a stable clock frequency
we could get rid of the 74123 monoflop and the rc oscillator built
around 7407. Although theese probably cause no problem whatsoever it's
always nice to get rid of analogue timing stuff in a digital circuit.

> > Btw for how long will a computer wait if DAT is held low?
> > Indefinitely or a few seconds?
> forever, as I recall.

Good.

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