Re: 8088 card and bank 15

Den Thu, 26 Oct 2017 21:29:18 +0100 skrev smf <smf@null.net>:
> On 26/10/2017 21:08, Michał Pleban wrote:
> 
> > Also, if the 8088 was allowed to touch bank 15, it would immediately
> > crash the 6509 which lives there. There is no possibility to stop
> > the 6509; the AEC signal, though present on the chip, is not
> > exposed on the expansion connector (in fact it is not connected
> > anywhere in the CBM-II and it is quite likely that the motherboard
> > hardware would not support it even if ou piggybacked it).
> 
> How does it stop the 6509 from accessing the ram when the 8088 card
> is running, the bios functions appear to do that.

According to the schematics (using the 8256059 CBM-II HP schematics and
the 8088 schematics that were recently linked on this list):

The adress bus is switched this way:
On the 8088 board PB1 of both CIAs generate/read a signal called
_BUSY2_. (Not sure which one gnerates and which one reads, that must be
up to the software). That signal is fed onto the motherboard
and the first half of U02 (74S00 quad nand gate) switches out the
motherboards MUX and _MUX_ signals and makes the 74S153 dual 4-to-1
MUXes U27,U34,U28,U38 use EXTMA0-7 instead of A0-A15. The first half of
U73, 74S02 (quad nor gate) is still active making the 74S153 MUXes
switch in the refresh counter periodically. So the CBM-II motherboard
handles the refresh of DRAM while the 8088 board handles muxing RAS/CAS
onto the DRAM.

The data bus is switched this way:
On the CBM-II motherboard PB4 on 6525 U8 generates the signal DRAMON
which is fed to the data input on the second half of U95 74LS74 dual
d-type flip flop. This way the 6509 can enable and disable on-board
DRAM. But the 74LS74 is also forced to disable dram mode by the same
_BUSY2_ signal that controls the adress bus. The output of the 74LS74
is fed onto the gates in U49 that also checks if the 6509 is in bank 15,
then motherboard access to the dram is switched out anyway. U33,
74LS245, does the switching itself. 

The control signal DRAMR/W is switched out by U58 which also switches
out the bank signals that's fed both to the DRAM control and to the "is
6509 in bank 15" detector and the DRAM control, which as far as I can
tell seems to be used to enable the stuff in bank 15. With the 8088
enabled the 6509 probably sees bank 15 regardless which bank is
selected. This would be nice to have verified by someone with a working
machine with the 8088 card.

On the 8088 board the _BUSY2_ signal is also processed in some way to
generate the control signals to enable/disable U7 74LS245 buffer for
DRAM data bus and U8 74LS373 latch for the bank signals (those that
have 1 added to them by the 74LS283 4-bit adder) and also the same
adress signals without the adder, feeding the first half of U10 74LS20
dual quad input nand gate, which via an inverter in U2 74S04 generates
the SEG F signal.

That implies that when the 6509 has control of the DRAM then the 8088
will see it's bios rom everywhere in it's adress space.

Disassembly of both the 8088 bios and the 6509 binaries should reveal
which 6526 drives the _BUSY2_ signal and which only reads it.

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