Re: 6522 VIA inputs

Date: Sat, 22 Apr 2017 17:33:18 +0200
Message-Id: <>
> On 2017-04-22, at 17:19, wrote:

>>> driving a NMOS i/o line high is a big nono. just dont. its a common thing
>>> to do to connect several outputs together, forming a wired OR - when one
>>> of those outputs is driving high, the one trying to pull low will have a
>>> hard time doing it. even if it still may work, the signal timing will go
>>> poop

Well, in this particular case it is me who controls what gets connected where. Therefore such an "OR gate" is not going to be a problem. Although...

>> Eh? So far I though NMOS is very good at sinking current to GND, but not
>> at supplying current from Vcc. Looking at the datasheet for the 6526
>> supports this, the output driver can supply at most 1mA, but can sink
>> something in the range of 3mA.
>> So if you connect 2 NMOS outputs together, the one pulling the line LOW
>> will win. Also, on most NMOS outputs, you cannot disable the 'pullups'
>> (see output driver schematic for the 6522).
>> What you must not do is using a CMOS output set to HIGH and connect it
>> to an NMOS output set to LOW.

..., while I am not planning to have this kind of configuration, I can not exclude that e. g. a software bug accidentally configures the pins in such way.

> thats what i ment with "driving high". a NMOS output does never "drive high", 
> it only ever pulls low.

So in any case I take the safest/most "correct" way would be to just tri-state my outputs, while - in order to avoid potential issues with longer lines/wires - adding somewhat stronger (say 33k?) pull-ups on my own?

SD! -

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Received on 2017-04-22 16:02:02

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