Re: 6522 VIA inputs

From: Gerrit Heitsch <>
Date: Sat, 22 Apr 2017 17:12:10 +0200
Message-ID: <>
On 04/22/2017 04:35 PM, wrote:
> On Friday 21 April 2017, 21:40:17 wrote:
>>> It's perfectly acceptable to ignore the pull ups and drive 0v/5v.
>> I am not sure if I am not trying to overengineer but what causes my doubts
>> is that it's never 0V/5V, and especially never the same between different
>> families of devices, etc.  While pushing the (pulled-up) line LO is OK
>> because that's what it is meant to be done, the potential of the sourcing
>> output and the pulled-up line are almost certainly different so it will
>> have to cause some (unnecessary / unnecessarily higher) current flow
>> through the line, possibly adding to consumption, unwanted emissions, etc.
>> ... or are all those possible side-effects fully negligible and I am just
>> too paranoid here? ;-)
> driving a NMOS i/o line high is a big nono. just dont. its a common thing to
> do to connect several outputs together, forming a wired OR - when one of those
> outputs is driving high, the one trying to pull low will have a hard time
> doing it. even if it still may work, the signal timing will go poop

Eh? So far I though NMOS is very good at sinking current to GND, but not 
at supplying current from Vcc. Looking at the datasheet for the 6526 
supports this, the output driver can supply at most 1mA, but can sink 
something in the range of 3mA.

So if you connect 2 NMOS outputs together, the one pulling the line LOW 
will win. Also, on most NMOS outputs, you cannot disable the 'pullups' 
(see output driver schematic for the 6522).

What you must not do is using a CMOS output set to HIGH and connect it 
to an NMOS output set to LOW.


       Message was sent through the cbm-hackers mailing list
Received on 2017-04-22 16:00:07

Archive generated by hypermail 2.2.0.