Re: Switchless ROMs

From: David Wood <>
Date: Thu, 29 Dec 2016 13:45:54 -0500
Message-ID: <>
Is it possible to detect a delay without a clock?  I suppose this is also
not infallible since accelerators could trigger it.

On Thu, Dec 29, 2016 at 1:28 PM, Michał Pleban <> wrote:

> Hello!
> wrote:
> > If we want to keep compatibility - I am afraid the answer is "yes". A
> simple example: a program uses the RAM area under KERNAL as a temporary
> storage and reads from the consecutive addresses there. I know for a fact
> that such programs exist. So you would need to monitor the configuration
> bits or the _CS or ... The next example is copying KERNAL from ROM to RAM -
> lots of programs to this in order to modify a few things in the KERNAL.
> Here monitoring the _CS won't help as the program reads from ROM locations
> and you know what happens when you don't differentiate between the _RST
> induced reads and the same done by the program.
> This is a valid point. As Gerrit said, you cannot distinguish the CPU
> reading the reset vector during the RESET, and the CPU reading the reset
> vector as a part of some user code.
> So it looks like the only thing you can do is to hook some more control
> signals from SID or VIC.
> Regards,
> Michau.
>        Message was sent through the cbm-hackers mailing list

       Message was sent through the cbm-hackers mailing list
Received on 2016-12-29 19:00:52

Archive generated by hypermail 2.2.0.