On Sun, Aug 07, 2016 at 09:44:04PM +0200, Gerrit Heitsch wrote: > >http://segher.ircgeeks.net/vic-ii/8565-blocks.jpg > > > >(that is 8565, not *entirely* the same as 6567/6569, but I labeled the > >blocks here). > > > >This is 6569 (R3): > > > >http://retronn.de/imports/cbm_chips/vic2_overview_gray4.jpg > > > >and this is R1 (warning, huge): > > > >http://mail.lipsia.de/~enigma/vic2r1/fullvic_lowquality.jpg > > > >(not much has changed in R3). > > Likely some timing issues. Well, obviously the digital video signals were pinned out, like on the 8565 (see the octagonal pads at the right). This is for testing only I think, the drivers for those pads are very weak. > > 6566 6567 > >17 phi0 phi0 > >18 phiin #RAS > >19 phicol #CAS > >20 Vss Vss > >21 A0 phicol > >22 A1 phiin > >23 A2 A11 > >24 A3 A0/A7/A8 > >25 A4 A1/A8/A9 > >26 A5 A2/A9/A10 > >27 A6 A3/A10/A11 > >28 A7 A4/A11/A12 > >29 A8 A5/A12/A13 > >30 A9 A6/A13/1 > >31 A10 A7 > >32 A11 A8 > >33 A12 A9 > >34 A13 A10 > > Hm? What do you mean with the 3 Adress lines on a single pin of the > 6567? The schematics of the C64 only show 2 per adress line. row address / column address for 7-bit ram addressing / column address for 8-bit ram addressing. It is a metal mask option on the VIC chip. As you see the 7-bit is much neater. > >Btw, the RAS/CAS things are self-timed, using analogue delays, long > >inverter chains etc. > > There should be differences between R1 and R3 in this area since R1 > wants a 82pF Capacitor between CAS and GND while it's not needed for R3. Interesting! Segher Message was sent through the cbm-hackers mailing listReceived on 2016-08-07 21:00:23
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