Re: MAX Machine PLA

From: Segher Boessenkool <>
Date: Sun, 7 Aug 2016 14:23:10 -0500
Message-ID: <>
On Sun, Aug 07, 2016 at 02:38:09PM +0200, Gerrit Heitsch wrote:
> On 07/31/2016 04:48 PM, Segher Boessenkool wrote:
> >Same with VIC-II: the 6566 is a very nice and clean design (what I can
> >reconstruct from it anyway, I haven't seen an actual die photo)...  The
> >DRAM versions, not so very clean.
> The interesting part would be to compare the 6566 and 6567 dies to see 
> what was changed and how much is the same. Where did they squeeze in the 
> refresh counter, the RAS/CAS logic, were things moved around for it...

(that is 8565, not *entirely* the same as 6567/6569, but I labeled the
blocks here).

This is 6569 (R3):

and this is R1 (warning, huge):

(not much has changed in R3).

Refresh counter sits next to the VM counters (it also writes the low
address bits, and the VM counters were handily on the end of things

Here's a piece of the pinout, including all changed signals:

	6566	6567
17	phi0	phi0
18	phiin	#RAS
19	phicol	#CAS
20	Vss	Vss
21	A0	phicol
22	A1	phiin
23	A2	A11
24	A3	A0/A7/A8
25	A4	A1/A8/A9
26	A5	A2/A9/A10
27	A6	A3/A10/A11
28	A7	A4/A11/A12
29	A8	A5/A12/A13
30	A9	A6/A13/1
31	A10	A7
32	A11	A8
33	A12	A9
34	A13	A10

So, phicol and phiin were moved (colour clock and dot clock inputs).
Note the weird routing of the current colour clock stuff, and the wacko
block at the start of the signal.  Those would make a much neater layout
in the original location.

Note all the address bus routing on the new layout; a lot of it is very
ad-hoc and strange.  Things would fit great with the original pinout.

The clock gen / redriving and the colour buffer ("C bits") seems very
untidy as well, but I cannot figure out how it should have more logically
been before.

Btw, the RAS/CAS things are self-timed, using analogue delays, long
inverter chains etc.

I want die pictures of the 6566, too :-)


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Received on 2016-08-07 20:00:13

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