Re: FPGATED

From: Hegedűs István <*hegedusis_at_t-online.hu*> Date: Sat, 23 Jul 2016 23:27:10 +0200 Message-ID: <0DD1989A05A3410580BAB9D41360AF31@emea.hpqcorp.net> · hegedusis_at_t-online.hu

Hi,

I believe that should be much easier. It can be done in a GODIL (I just 
don't have one but I will buy).
My FPGATED has the 8501 shell written around fpga64's 6502 core. It is a 
good starting point however I have to think how to implement hold times when 
the FPGA runs on phi0 instead of the higher 28MHz (4*dor clock) internal 
clock.
Othe roption is to synchronize the FPGA clock to phi0. Probably that is the 
way to go. I will work on it later.

Istvan

-----Original Message----- 
From: Gerrit Heitsch
Sent: Friday, July 22, 2016 4:45 PM
To: cbm-hackers@musoftware.de
Subject: Re: FPGATED

On 07/22/2016 02:16 AM, Steve Gray wrote:
> Very nice! I'm looking forward to a drop-in replacement. I have a few
> Plus/4's that could use a new TED.

Next project would be a replacement 8501 since those also die easily...

  Gerrit

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